Design Verification Engineer
ISRAEL / R&D / FULL-TIME
Background
We are expanding our Design Verification team, and invite you to explore Space with us!
The job includes taking a viable role in the VLSI verification tasks of Ramon.Space line of products.
What you will be doing
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Define the DV plan including DV requirements, Architecture, Test plan and deliverables.
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Implementation of UVM / DVE components.
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Conduct status and progress review
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Take part of block level to full chip/FPGA level DV, including Debug and GLS.
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Develop scripts in various scripting languages for supporting the DV / VLSI automation.
Requirements
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Experienced Design Verification Engineer with Solid DV background.
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Hands on with Definition and Execution of DV Test benches in UVM, System Verilog.
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Hands on and ownership of DV module verification from definition to Signoff.
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Solid knowhow of ASIC and FPGA design flow.
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Solid knowhow of Digital System Design.
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Independent, team player with good team spirit